Integrated circuits are very complex devices that include multiple layers. Each layer may include conductive material, isolating material and/or semi-conductive materials. These various materials are arranged in patterns, usually in accordance with the expected functionality of the integrated circuit. The patterns also reflect the manufacturing process of the integrated circuits.
Conductive layers usually include conductors made of conductive materials, whereas the conductors are separated by isolating materials such as various oxides. The dielectric layers are located between the conductive layers in an interlaced manner. Conductors of distinct conductive layers may be connected to each other and/or to the substrate by conductive materials (termed interconnects or vias) located within the dielectric layers. The substrate may include semi-conducting materials and at least a portion of the substrate is connected to a virtual ground.
Various inspection and failure analysis techniques evolved for inspecting integrated circuits both during the fabrication stages, between consecutive manufacturing stages, either in combination with the manufacturing process (also termed “in line” inspection techniques) or not (also termed “off line” inspection techniques). Various optical as well as charged particle beam inspection tools and review tools are known in the art, such as the Compluss™ and SEMVision™ of Applied Materials Inc. of Santa Clara, Calif.
Manufacturing failures may affect the electrical characteristics of the integrated circuits. Some of these failures result from unwanted disconnections between various elements of the integrated circuits. An under-etched via or conductor can be floating instead of being connected to a conducting sub-surface structure.
Such a failure can be detected due to charging differences between said defective structure and non-defective structures. In order to facilitate voltage contrast analysis there must be a charging difference between the defective structure and its surroundings.
Typically the sub-surface structure is electrically connected to the substrate of the wafer or is otherwise connected to an external voltage source or to the ground. Thus, the charging of the structure surrounding can be relatively easily controlled.
The charging of the wafer is usually controlled with an electrode (also known as charge control plate or CCP) positioned above the wafer and held at either a positive or negative voltage as shown in FIG. 1. In order to assure proper charging control the inspected structures (or at least the non-defective structures) are connected to the ground or to some reference voltage source.
U.S. Pat. No. 6,627,884 of McCord, et al. titled “Simultaneous flooding and inspection for charge control in an electron beam inspection machine”, and U.S. Pat. No. 6,586,736 of McCord titled “Scanning electron beam microscope having an electrode for controlling charge build up during scanning of a sample”, which are incorporated herein by reference describe systems that include a charge control plate.
Various wafers such as silicon over insulator (SOI) wafers and short loop wafers have sub surface structures that are intentionally floating. Thus, scanning the wafers with a charged particle causes charging effects that are hard to manage.
FIG. 1 illustrates a cross section of a typical prior art SOI wafer. The lowest layer is a substrate 210. The substrate is usually made of silicon. An oxide layer (also referred to as BOX) 220 is manufactured above the substrate 210. The upper layer of the SOI wafer includes an inter-dielectric layer 240 through which contact holes were fabricated and then filled with conductive structures (also termed conductors) 250 such as vias, metal lines and the like. Trench insulators, such as oxide-made trench insulators 260 as well as silicon epilayer islands 230, 232 and 234, that are insulated from each other by trench isolators 260 are formed between the inter-dielectric layer 240 and the oxide layer 220.
Non-defective conductors are connected to the silicon epilayer islands while defective conductors are isolated from said islands.
During electron beam inspection of the SOI wafer each of the epilayer islands 230, 232 and 234 acts like a capacitor and is charged to a certain voltage level. This charge does not discharge through the substrate 210 because each island is isolated, by the oxide layer 220 and trench insulators 260.
Many conductors 250 are connected to each silicon epilayer island. Thus, a charge that is built as a result of scanning some conductors affects the charge of conductors that were not yet scanned. Once the SEM 10 scans the latter conductors the contrast between them and their vicinity can be dramatically reduced and even eliminated.
There is a need to provide a system and method for an effective voltage contrast analysis, especially in the presence of severe charging effects.